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ME7750A - Anritsu Bit Error Rate Testers

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ME7750A - Anritsu Bit Error Rate Testers


12.50Gbps (Max. Data Rate)

The Anritsu ME7750A is the low cost 43.5 Gb/s BER test solution, ideal for research, development and manufacturing testing of Gigabit light-wave and digital devices, components and subsystems. The system generates and analyses data streams from 25 Gb/s to 43.5 Gb/s. Also, the ME7750A BERT system can be used to test 40 G-bit transceivers, modulators, MUX/DEMUX, high-speed logic devices, optical module and forward error correction (FEC) rates beyond 40 Gb/s. These capabilities give the users the breadth of applications that thoroughly test and characterise their devices for a complete confidence in their product performance and quality.

The ME7750A BERT system consists of the existing popular MP1758A (4-Channel Pulse Pattern Generator), MP1801A (MUX), MP1802A (DEMUX), MP1776A (4-Channel Error Detector) and an external signal source. The transmitter side of the output signal is composed of a signal generator (Anritsu'''''''s 69B Series synthesiser) for generating the clock signal, a pulse pattern generator (MP1758A) for generating four channels of 10 Gb/s data patterns, and a 4:1 multiplexer (MP1801A) for multiplexing these signals into a 43.5 Gbit/s signal. The receiver side is composed of a 1:4 demultiplexer (MP1802A) for splitting the 43.5 Gbit/s signal into four channels, and an error detector (MP1776A) for measuring the error rate of the four channels. The phase of each channel is shifted º cycle which enables multiplexed signal to a pure PRBS stream.

  • Wide operation frequency from 25 Gb/s to 43.5 Gb/s covering standard FEC and non-FEC rates
  • 4-channel simultaneous parallel testing from 100 Mb/s to 12.5 Gb/s with the MP1758A and the MP1776A
  • †4:1 MUX and 1:4 DEMUX testing with the MP1801A and the MP1802A
  • 40 Gb/s Optical system testing with the MP9681A and the MP9682A
  • Independent level adjustment for each of the 4-channels of the PPG
  • Measurement with pure PRBS pattern
  • Programmable Pattern, PRBS and Inverted PRBS Pattern: 2n-1 (n = 7, 9, 11, 15, 20, 23, 31)
  • High quality data output waveform, low jitter and low distortion
  • Cross-Point Adjustment capability on the MP1758A (4-channel PPG)
  • Independent mode and Simultaneous BER testing/analysis up to 4-channel with the MP1776A
  • Testing of SONET/SDH frames up to OC-48c/STM-16c, CID Pattern with the MX177601A software
  • Excellent operability with Front Panel Keys, Easy-to-use, Intuitive


Specifications
Max. Data Rate
12.50Gbps

Max. Clock Rate
n/a

Pattern Depth
Programmable data: max. 8Mbits (Independent mode), 16Mbits (2ch combined mode), 32Mbits (4ch combined mode)

More Details
BERT System

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